Analysable instruction memories for hard real-time systems

In safety-critical embedded real-time systems the timing behaviour is of highest importance, because applications underlie timing constraints that have to be met. Otherwise the system might fail causing harm to humans, the environment, or the system itself. Therefore, such hard real-time systems have to provide timing guarantees. Since the timing behaviour of the system does not only depend on the application itself and is also determined by the particular hardware, there is a need for predictable hardware architectures, as e.g. pipelines or memories. Within this work the focus is on first level instruction memories, which have a large influence on the performance of the system. So a predictable instruction fetch guaranteed by a timing predictable instruction memory hierarchy is crucial for a design of a safety-critical real-time system. In this work the so called dynamic instruction scratchpad (D–ISP) is proposed and its impact on hard real-time systems is examined. The D–ISP features a function-based dynamic content management that ensures that the currently executed function is always contained in the scratchpad. Hence, it guarantees a predictable and instantaneous instruction fetch, once the active function is loaded. Moreover, the D–ISP eases the timing analysis of the whole system by eliminating the interferences between instruction and data memory access. For evaluation the D–ISP was verified in a cycle-accurate SystemC model and implemented into an FPGA using the hardware description language VHDL. The D–ISP was integrated into the CarCore processor, which is instruction set compatible to the Infineon TriCore, and it was used as predictable first level instruction memory of the MERASA multicore. An examination of the hardware complexity showed that the D–ISP is more hardware intense than common cache memories, but the costs are in the same order of magnitude. The advantages of the D–ISP implementation compared to a cache are the decoupling of the content and management memory structures and its minimal influence on the timing of the fetch path. To evaluate the impact of the D–ISP on the WCET estimates of the system a static timing analysis of the D–ISP and the CarCore host processor was performed. It could be shown that in comparison to other common instruction memories like caches and scratchpads with fixed content the D–ISP can provide lower WCET estimates. It can reach an up to 14% lower WCET estimate in comparison to scratchpads with fixed content and reduce the WCET estimate compared to a fully associative LRU cache by at most 29%. Furthermore, different replacement policies for the D–ISP were compared. It is shown that the FIFO replacement policy requires the lowest hardware effort, but cannot reach the WCET estimates that an LRU or a stack-based replacement policy can provide. In general the LRU policy performs best, but it cannot be implemented in hardware. The stack-based replacement policy requires up to 25% more hardware effort than the implementation of the FIFO replacement policy, but reaches similar WCET estimates as LRU. With the D–ISP a promising alternative to common first level instruction memories for safety-critical real-time systems is proposed. The performed evaluations were able to quantify the impact of the D–ISP on the hardware complexity, the WCET estimates, and the average case performance of the system.